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| 1. general description the greenchip iii is the third generation of green switched mode power supply (smps) controller ics. the tea1750 combines a controller for power factor correction (pfc) and a ?yback controller. its high level of integration allows the design of a cost-effective power supply with a very low number of external components. the special built-in green functions provide high ef?ciency at all power levels. this applies to quasi-resonant operation at high power levels, quasi-resonant operation with valley skipping, as well as to reduced frequency operation at lower power levels. at low power levels, the pfc switches over to burst mode control to maintain high ef?ciency. in burst mode, soft-start and soft-stop functions are added to eliminate audible noise. during low power conditions, the ?yback controller switches to frequency reduction mode and limits the peak current to 25 % of its maximum value. this will ensure high ef?ciency at low power and good standby power performance while minimizing audible noise from the transformer. the proprietary high voltage bcd800 process makes direct start-up possible from the recti?ed universal mains voltage in an effective and green way. a second low voltage silicon on insulator (soi) ic is used for accurate, high speed protection functions and control. the tea1750 enables highly ef?cient and reliable supplies with power requirements up to 250 w, to be designed easily and with the minimum number of external components. 2. features 2.1 distinctive features n integrated pfc and ?yback controller n universal mains supply operation (70 v ac to 276 v ac) n high level of integration, resulting in a very low external component count and a cost-effective design 2.2 green features n on-chip start-up current source 2.3 pfc green features n valley/zero voltage switching for minimum switching losses (patented) n frequency limitation to reduce switching losses n burst mode operation if a low load is detected at the ?yback output (patented) tea1750 greenchip iii smps control ic rev. 02 15 december 2008 product data sheet
tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 2 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 2.4 flyback green features n valley switching for minimum switching losses (patented) n frequency reduction with ?xed minimum peak current at low power operation to maintain high ef?ciency at low output power levels 2.5 protection features n safe restart mode for system fault conditions n continuous mode protection by means of demagnetization detection for both converters (patented) n undervoltage protection (uvp) (foldback during overload) n accurate overvoltage protection (ovp) for both converters (adjustable for ?yback converter) n open control loop protection for both converters n ic overtemperature protection (otp) n low and adjustable overcurrent protection (ocp) trip level for both converters n soft (re)start for both converters n soft stop pfc to minimize audible noise n mains undervoltage protection (uvp)/ brownout protection n general purpose input for latched protection, e.g. to be used for system overtemperature protection 3. applications n the device can be used in all applications that require an ef?cient and cost-effective power supply solution up to 250 w. notebook adapters in particular can bene?t from the high level of integration. 4. ordering information table 1. ordering information type number package name description version tea1750t so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 3 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 5. block diagram fig 1. block diagram low vin timer 50 m s timer 4 m s pfc prot voovp voburst high voburst low vostart fb voshort lowvin ocp pfc driver enable pfc start stop pfc 500 mv voburst low voburst high soft start soft stop pfcgate valley detect zcs - 100 mv blank 2.50 v 2.7 v 1.25 v max vcc good vostart fb low power ext prot ext prot otp ovpfb latch reset ton max voshort timeout v uvlo prot ext prot v start v uvlo smps control latched protection safe restart protection charge control startfb start stop pfc prot v cc good charge s s s r s s s r pfc osc pfc prot prot latch reset enable pfc r s q start soft start fb fb driver enable fb blank q r s pfc osc ton max freq red. ext prot low power time out fb driver fb gate drv drv 12 13 pfc driver pfc gate vinsense pfccomp vosense pfcsense pfcaux otp change valley detect otp internal supply zcs fb gate fbaux fbsense counter ovp ovpfb 1.12 v 3.5 v 7 6 11 8 9 hv v cc 16 1 gnd 5 3 10 4 fbctrl latch 80 mv pfcdriver fbdriver v start v uvlo 2 30 m a 60 m a 60 m a 3.7 v 80 m a prot enablefb 2.5 v 3.5 v 1.25 v 014aaa055 temp tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 4 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for tea1750t (sot109-1) tea1750t vcc hv gnd hvs fbctrl hvs fbaux fbdriver latch pfcdriver pfccomp pfcsense vinsense fbsense pfcaux vosense 014aaa015 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description v cc 1 supply voltage gnd 2 ground fbctrl 3 control input for ?yback fbaux 4 input from auxiliary winding for demagnetization timing and overvoltage protection for ?yback latch 5 general purpose protection input pfccomp 6 frequency compensation pin for pfc vinsense 7 sense input for mains voltage pfcaux 8 input from auxiliary winding for demagnetization timing for pfc vosense 9 sense input for pfc output voltage fbsense 10 programmable current sense input for ?yback pfcsense 11 programmable current sense input for pfc pfcdriver 12 gate driver output for pfc fbdriver 13 gate driver output for ?yback hvs 14, 15 high voltage safety spacer, not connected hv 16 high voltage start-up and valley sensing of ?yback part tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 5 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7. functional description 7.1 general control the tea1750 contains a controller for a power factor correction circuit as well as a controller for a ?yback circuit. a typical con?guration is shown in figure 3 . 7.1.1 start-up and undervoltage lock-out initially the capacitor on the v cc pin is charged from the high voltage mains via the hv pin. as long as v cc is below v trip , the charge current is low. this protects the ic in case the v cc pin is shorted to ground. for a short start-up time the charge current above v trip is increased until v cc reaches v th(uvlo) . if v cc is between v th(uvlo) and v startup , the charge current is low again, ensuring a low duty cycle during fault conditions. the control logic activates the internal circuitry and switches off the charge current when the voltage on pin v cc passes the v startup level. first, the latch pin output is activated and the soft-start capacitors on the pfcsense and fbsense pins are charged. when the latch pin voltage exceeds the v en(latch) voltage and the soft-start capacitor on the pfcsense pin is charged, the pfc circuit is activated. the supply current from the hv pin is then switched on again and the pfc circuit charges the c bus capacitor. when the voltage on pin vosense reaches the v start(fb) level, the charge current is switched off and the ?yback converter is activated (providing the soft-start capacitor on the fbsense pin is charged). the output voltage of the ?yback converter is then regulated to its nominal output voltage. the ic supply is taken over by the auxiliary winding of the ?yback converter. see figure 4 . fig 3. typical con?guration of tea1750 12 11 9 16 13 8 6 7 3 2 10 4 1 tea1750t 014aaa016 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 6 of 29 nxp semiconductors tea1750 greenchip iii smps control ic when the pfc is started, there is initially no supply take-over from the auxiliary winding. to make a small v cc capacitor possible, the v cc voltage is regulated to the v startup level, as long as the ?yback converter has not yet started. regulation is done by hysteretic control with a limited (high level) charge current. the hysteresis is typically 300 mv. if during start-up the latch pin does not reach the v en(latch) level before v cc reaches v th(uvlo) , the latch pin output is de-activated and the charge current is switched on again. as soon as the ?yback converter is started, the voltage on the fbctrl pin is monitored. if the output voltage of the ?yback converter does not reach its intended regulation level in a prede?ned time, the voltage on the fbctrl pin reaches the v to(fbctrl) level and an error is assumed. the tea1750 then initiates a safe restart. when one of the protection functions is activated, both converters stop switching and the v cc voltage drops to v th(uvlo) . a latched protection recharges the v cc capacitor via the hv pin, but does not restart the converters. for a safe-restart protection, the capacitor is recharged via the hv pin and the device restarts (see figure 1 ) in the event of an overvoltage protection of the pfc circuit (v i on pin vosense > v ovp(vosense) ), only the pfc controller stops switching until the vosense pin voltage drops below v ovp(vosense) again. also, if a mains undervoltage is detected (v i on pin vinsense < v stop(vinsense) ), only the pfc controller stops switching until v i on pin vinsense > v start(vinsense) again. when the voltage on pin v cc drops below the undervoltage lock-out level, both controllers stop switching and re-enter the safe restart mode. in the safe restart mode the driver outputs are disabled and the v cc pin voltage is recharged via the hv pin. tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 7 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.1.2 supply management all internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit. 7.1.3 latch input pin latch is a general purpose input pin, which can be used to switch off both converters. the pin sources a current, i o(latch) on pin latch (typ 80 m a). switching of both converters is stopped as soon as the voltage on this pin drops below 1.25 v. at initial start-up, switching is inhibited until the voltage on the latch pin is above 1.35 v (typ). no internal ?ltering is done on this pin. an internal zener clamp of 2.7 v (typ) protects this pin from excessive voltages. fig 4. start-up sequence, normal operation, and re-start sequence i hv v cc latch protection pfcsense pfcdriver fbsense fbdriver fbctrl vosense v out charging vcc capacitor starting converters normal operation protection restart soft start soft start vinsense v startup v th(uvlo) v trip v en(latch) v to(fbctrl) v start(fb) v start(vinsense) 014aaa060 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 8 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.1.4 fast latch reset in a typical application, the mains can be interrupted brie?y to reset the latched protection. the pfc bus capacitor, c bus , does not have to discharge for this latched protection to reset. typically the pfc bus capacitor, c bus , has to discharge for the v cc to drop to this reset level. when the latched protection is set, the clamping circuit of the vinsense circuit is disabled (see also section 7.2.8 ). as soon as the vinsense voltage drops below 750 mv (typ) and then is raised to 870 mv (typ), the latched protection is reset. the latched protection will also be reset by removing both the voltage on pin v cc and on pin hv. 7.1.5 overtemperature protection (otp) an accurate internal temperature protection is provided in the circuit. when the junction temperature exceeds the thermal shutdown temperature, the ic only stops switching. as long as otp is active, the v cc capacitor is not recharged from the hv mains. the otp circuit is supplied from the hv pin if the v cc supply voltage is not suf?cient. otp is a latched protection. it can be reset by removing both the voltage on pin v cc and on pin hv or by the fast latch reset function, see section 7.1.4 7.2 power factor correction circuit the power factor correction circuit operates in quasi-resonant or discontinuous conduction mode with valley switching. the next primary stroke is only started when the previous secondary stroke has ended and the voltage across the pfc mosfet has reached a minimum value. the voltage on the pfcaux pin is used to detect transformer demagnetization and the minimum voltage across the external pfc mosfet switch. 7.2.1 t on control the power factor correction circuit is operated in t on control. the resulting mains harmonic reduction of a typical application is well within the class-d requirements. 7.2.2 valley switching and demagnetization (pfcaux pin) the pfc mosfet is switched on after the transformer is demagnetized. internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mosfet. the next stroke is started if the voltage across the pfc mosfet is at its minimum in order to reduce switching losses and electromagnetic interference (emi) (valley switching). if no demagnetization signal is detected on the pfcaux pin, the controller generates a zero current signal (zcs), 50 m s (typ) after the last pfc gate signal. if no valley signal is detected on the pfcaux pin, the controller generates a valley signal 4 m s (typ) after demagnetization was detected. to protect the internal circuitry, for example during lightning events, it is advisable to add a5k w series resistor to this pin. to prevent incorrect switching due to external disturbance, the resistor should be placed close to the ic on the printed circuit board. tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 9 of 29 nxp semiconductors tea1750 greenchip iii smps control ic for applications with high transformer ringing frequencies (after the secondary stroke), the pfcaux pin should be connected via a capacitor and a resistor to the auxiliary winding. a diode must than be placed from the ground connection to the pfcaux pin. 7.2.3 frequency limitation to optimize the transformer and minimize switching losses, the switching frequency is limited to f sw(pfc)max . if the frequency for quasi-resonant operation is above the f sw(pfc)max limit, the system switches over to discontinuous conduction mode. also here, the pfc mosfet is only switched on at a minimum voltage across the switch (valley switching). 7.2.4 mains voltage compensation (vinsense pin) the mathematical equation for the transfer function of a power factor corrector contains the square of the mains input voltage. in a typical application this results in a low bandwidth for low mains input voltages, while at high mains input voltages the mains harmonic reduction (mhr) requirements may be hard to meet. to compensate for the mains input voltage in?uence, the tea1750 contains a correction circuit. via the vinsense pin the average input voltage is measured and the information is fed to an internal compensation circuit. with this compensation it is possible to keep the regulation loop bandwidth constant over the full mains input range, yielding a fast transient response on load steps, while still complying with class-d mhr requirements. in a typical application, the bandwidth of the regulation loop is set by a resistor and two capacitors on the pfccomp pin. 7.2.5 soft start-up (pin pfcsense) to prevent audible transformer noise at start-up or during hiccup, the transformer peak current, i dm , is increased slowly by the soft start function. this can be achieved by inserting r ss1 and c ss1 between pin pfcsense and current sense resistor, r sense1 . an internal current source charges the capacitor to v pfcsense =i start(soft)pfc r ss1 . the voltage is limited to v start(soft)pfc . the start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of r ss1 and c ss1 . the charging current i start(soft)pfc ?ows as long as the voltage on pin pfcsense is below 0.5 v (typ). if the voltage on pin pfcsense exceeds 0.5 v, the soft start current source starts limiting current i start(soft)pfc . as soon as the pfc starts switching, the i start(soft)pfc current source is switched off; see figure 5 . t softstart 3r ss1 c ss1 = tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 10 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.2.6 burst mode control when the output power of the ?yback converter (see section 7.3 ) is low, the ?yback converter switches over to frequency reduction mode. when frequency reduction mode is entered by the ?yback controller, the power factor correction circuit switches to burst mode control. in burst mode control, switching of the power factor correction circuit is inhibited until the voltage on the vosense pin has dropped to v burst(l) . switching then restarts with a soft-start to avoid audible noise (see section 7.2.5 ). as soon as the voltage on the vosense pin reaches v burst(h) the soft-stop circuit is activated, again to avoid audible noise. during the soft-stop time the output voltage of the power factor correction circuit overshoots, depending on the soft-start resistor and capacitor, r ss1 and c ss1, on the pfcsense pin. as the v burst(h) voltage is well below the v reg(vosense) voltage, the pfc output voltage does not reach the normal operation output voltage of the power factor correction circuit in a typical application due to this overshoot. the burst mode repetition rate is de?ned by the output power and the value of the bus capacitor, c bus . during burst mode operation the pfccomp pin is clamped between a voltage of 2.7 v (typ) and 3.9 v (typ). the lower clamp voltage limits the maximum power that is delivered during burst mode operation and yields a more sinusoidal input current during the burst pulse. the upper clamp voltage ensures that the pfc can return to its normal regulation point in a limited amount of time when returning from burst mode. as soon as the ?yback converter leaves frequency reduction mode, the power factor correction circuit restores normal operation. to prevent continuous on and off switching of the pfc circuit, a small hysteresis is built in (50 mv (typ) on the fbctrl pin). fig 5. soft start-up and soft stop of pfc soft start soft stop control ocp + 11 pfcsense 0.5 v i start(soft)pfc 60 m a s1 r ss1 c ss1 r sense1 014aaa018 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 11 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.2.7 overcurrent protection (pfcsense pin) the maximum peak current is limited cycle-by-cycle by sensing the voltage across an external sense resistor (r sense1 ) on the source of the external mosfet. the voltage is measured via the pfcsense pin. 7.2.8 mains undervoltage lock-out / brownout protection (vinsense pin) to prevent the pfc from operating at very low mains input voltages, the voltage on the vinsense pin is sensed continuously. as soon as the voltage on this pin drops below the v stop(vinsense) level, switching of the pfc is stopped. if the low mains situation continues, the pfc bus voltage eventually drops. the voltage on the vosense pin then drops below the v start(fb) level and the ?yback converter is also disabled. the voltage on pin vinsense is clamped to a minimum value, (v start(vinsense) -d v pu(vinsense) ) for a fast restart as soon as the mains input voltage is restored after a mains dropout. 7.2.9 overvoltage protection (vosense pin) to prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. as soon as the voltage on the vosense pin exceeds the v ovp(vosense) level, switching of the power factor correction circuit is inhibited. switching of the pfc recommences as soon as the vosense pin voltage drops below the v ovp(vosense) level again. when the resistor between pin vosense and ground is open, the overvoltage protection is also triggered. 7.2.10 pfc open loop protection (vosense pin) the power factor correction circuit does not start switching until the voltage on the vosense pin is above the v th(ol)(vosense) level. this protects the circuit from open loop and vosense short situations. as the vosense pin draws a small input current, switching is also inhibited when the pin is left open. fig 6. burst mode control v burst(h) v burst(l) soft-stop ton control soft-start v vosense envelop of peak current 014aaa019 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 12 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.2.11 driver (pin pfcdriver) the driver circuit to the gate of the power mosfet has a current sourcing capability of typically 500 ma and a current sink capability of typically 1.2 a. this permits fast turn-on and turn-off of the power mosfet for ef?cient operation. 7.3 flyback controller the tea1750 includes a controller for a ?yback converter. the ?yback converter operates in quasi-resonant or discontinuous conduction mode with valley switching. the auxiliary winding of the ?yback transformer provides demagnetization detection and powers the ic after start-up. 7.3.1 multi mode operation the tea1750 ?yback controller can operate in multi modes; see figure 7 . at high output power the converter switches to quasi-resonant mode. the next converter stroke is started after demagnetization of the transformer current. in quasi-resonant mode switching losses are minimized as the converter only switches on when the voltage across the external mosfet is at its minimum (valley switching, see also section 7.3.2 ). to prevent high frequency operation at lower loads, the quasi-resonant operation changes to discontinuous mode operation with valley skipping in which the switching frequency is limited for emi to f sw(fb)(max) (125 khz typ). again, the external mosfet is only switched on when the voltage across the mosfet is at its minimum. at very low power and standby levels the frequency is controlled down by a voltage controlled oscillator (vco). the minimum frequency can be reduced to zero. during frequency reduction mode, the primary peak current is kept at a minimal level of ipkmax/4 to maintain a high ef?ciency. (ipkmax is the maximum primary peak current set by the sense resistor and the maximum sense voltage.) as the primary peak current is low in frequency reduction mode operation (ipk = ipkmax/4), no audible noise is noticeable at switching frequencies in the audible range. valley switching is also active in this mode. fig 7. multi mode operation ?yback discontinuous with valley switching quasi resonant pfc burst mode frequency reduction f sw(fb)max output power switching frequency 014aaa025 pfc on tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 13 of 29 nxp semiconductors tea1750 greenchip iii smps control ic in frequency reduction mode the pfc controller is switched to burst mode operation and the ?yback maximum frequency changes linearly with the control voltage on the fbctrl pin (see figure 8 ). for stable on-off switching of the pfc burst mode, the fbctrl pin has a 50 mv (typ) hysteresis. at no load operation the switching frequency of the ?yback can be reduced to (almost) zero. 7.3.2 valley switching (hv pin) refer to figure 9 . a new cycle starts when the external mosfet is activated. after the on-time (determined by the fbsense voltage and the fbctrl voltage), the mosfet is switched off and the secondary stroke starts. after the secondary stroke, the drain voltage shows an oscillation with a frequency of approximately where l p is the primary self inductance of the ?yback transformer and c d is the capacitance on the drain node. as soon as the internal oscillator voltage is high again and the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. figure 9 shows the drain voltage, valley signal, secondary stroke signal and the internal oscillator signal. valley switching allows high frequency operation as capacitive switching losses are reduced, see equation 1 . high frequency operation makes small and cost-effective magnetics possible. (1) fig 8. frequency control of ?yback part f sw(fb)max v fbctrl 1.5 v discontinuous with valley switching quasi resonant frequency reduction pfc burst mode switching frequency 014aaa026 pfc on 1 2 p l p c d () () --------------------------------------------------- - p 1 2 -- - c d v 2 f = ? ?? tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 14 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.3.3 current mode control (fbsense pin) current mode control is used for the ?yback converter for its good line regulation. the primary current is sensed by the fbsense pin across an external resistor and compared with an internal control voltage.the internal control voltage is proportional to the fbctrl pin voltage. (1) start of new cycle at lowest drain voltage. (2) start of new cycle in a classical pulse width modulation (pwm) system without valley detection. fig 9. signals for valley switching drain secondary stroke 014aaa027 secondary ringing primary stroke valley (2) (1) secondary stroke oscillator tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 15 of 29 nxp semiconductors tea1750 greenchip iii smps control ic the driver output is latched in the logic, preventing multiple switch-on. 7.3.4 demagnetization (fbaux pin) the system is always in quasi-resonant or discontinuous conduction mode. the internal oscillator does not start a new primary stroke until the previous secondary stroke has ended. demagnetization features a cycle-by-cycle output short-circuit protection by immediately lowering the frequency (longer off-time), thereby reducing the power level. demagnetization recognition is suppressed during the ?rst t sup(xfmr_ring) time (2 m s typ). this suppression may be necessary at low output voltages and at start-up and in applications where the transformer has a large leakage inductance. if pin fbaux is open-circuit or not connected, a fault condition is assumed and the converter stops operating immediately. operation restarts as soon as the fault condition is removed. 7.3.5 flyback control / time-out (fbctrl pin) the pin fbctrl is connected to an internal voltage source of 3.5 v via an internal resistor (typical resistance is 3 k w ). as soon as the voltage on this pin is above 2.5 v (typ), this connection is disabled. above 2.5 v the pin is biased with a small current. when the voltage on this pin rises above 4.5 v (typ), a fault is assumed and switching is inhibited. when a small capacitor is connected to this pin, a time-out function can be created to protect against an open control loop situation (see figure 11 and figure 12 ). the time-out function can be disabled by connecting a resistor (100 k w ) to ground on the fbctrl pin. if the pin is shorted to ground, switching of the ?yback controller is inhibited. in normal operating conditions, when the converter is regulating the output voltage, the voltage on the fbctrl pin is between 1.4 v and 2.0 v (typical values) from minimum to maximum output power. fig 10. frequency control of ?yback part v sense(fb)max v fbctrl 1.5 v 2.0 v 0.52 v flyback frequency reduction pfc burst mode fbsense peak voltage 014aaa028 pfc on flyback discontinuous or qr flyback cycle skip mode 1.4 v 0.13 v tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 16 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.3.6 soft start-up (pin fbsense) to prevent audible transformer noise during start-up, the transformer peak current, i dm is slowly increased by the soft start function. this can be achieved by inserting a resistor and a capacitor between pin fbsense and the current sense resistor. an internal current source charges the capacitor to v = i start(soft)(fb) xr ss2 , with a maximum of approximately 0.5 v. the start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of r ss2 and c ss2 . the soft start current i start(soft)(fb) is switched on as soon as v cc reaches v startup . when the voltage on the vosense pin reaches the v start(fb) level and the voltage on pin fbsense has reached 0.5 v, the ?yback converter starts switching. the soft start current ?ows as long as the voltage on pin fbsense is below approximately 0.5 v. if the voltage on pin fbsense exceeds 0.5 v, the soft start current source starts limiting the current. after the ?yback converter has started, the soft start current source is switched off. a. circuit diagram b. timing diagram fig 11. time-out protection 014aaa049 fbctrl 2.5 v 4.5 v 30 m a 3 k w 3.5 v timeout 014aaa050 4.5 v 2.5 v v fbctrl output voltage intended output voltage not reached within time-out time. intended output voltage reached within time-out time. restart t softstart 3r ss2 c ss2 = tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 17 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.3.7 maximum on-time the ?yback controller limits the on-time of the external mosfet to 25 m s (typ). when the on-time is longer than 25 m s, the ic stops switching and enters the safe restart mode. 7.3.8 overvoltage protection (fbaux pin) an output overvoltage protection is implemented in the greenchip iii series. this works for the tea1750 by sensing the auxiliary voltage via the current ?owing into pin fbaux during the secondary stroke. the auxiliary winding voltage is a well-de?ned replica of the output voltage. voltage spikes are averaged by an internal ?lter. if the output voltage exceeds the ovp trip level, an internal counter starts counting subsequent ovp events. the counter has been added to prevent incorrect ovp detection which might occur during electrostatic discharge (esd) or lightning events. if the output voltage exceeds the ovp trip level a few times and not again in a subsequent cycle, the internal counter counts down at twice the speed it uses when counting up. however, when typically 8 cycles of subsequent ovp events are detected, the ic assumes a true ovp and the ovp circuit switches the power mosfet off. as the protection is latched, the converter only restarts after the internal latch is reset. in a typical application the mains should be interrupted to reset the internal latch. the output voltage v ovp(fbaux) at which the ovp function trips, can be set by the demagnetization resistor, r fbaux : where n s is the number of secondary turns and n aux is the number of auxiliary turns of the transformer. current i ovp(fbaux) is internally trimmed. the value of r fbaux can be adjusted to the turns ratio of the transformer, thus making an accurate ovp detection possible. fig 12. soft start-up of ?yback 014aaa020 soft start control ocp + 10 fbsense 0.5 v i start(soft)fb 60 m a s2 r ss2 c ss2 r sense2 v o ovp () n s n aux ----------- - i ovp fbaux () r fbaux v clamp fbaux () + () = tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 18 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 7.3.9 overcurrent protection (fbsense pin) the primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor r sense2 . the ocp circuit limits the voltage on pin fbsense to an internal level (see also section 7.3.3 ). the ocp detection is suppressed during the leading edge blanking period, t leb , to prevent false triggering caused by switch-on spikes. 7.3.10 driver (pin fbdriver) the driver circuit to the gate of the external power mosfet has a current sourcing capability of typically 500 ma and a current sink capability of typically 1.2 a. this permits fast turn-on and turn-off of the power mosfet for ef?cient operation. 8. limiting values fig 13. ocp leading edge blanking leb (t leb ) ocp level v fbsense t 014aaa022 table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit voltages v cc supply voltage - 0.4 +38 v v latch voltage on pin latch current limited - 0.4 +5 v v fbctrl voltage on pin fbctrl - 0.4 +5 v v pfccomp voltage on pin pfccomp - 0.4 +5 v v vinsense voltage on pin vinsense - 0.4 +5 v v vosense voltage on pin vosense - 0.4 +5 v v pfcaux voltage on pin pfcaux - 25 +25 v v fbsense voltage on pin fbsense current limited - 0.4 +5 v v pfcsense voltage on pin pfcsense current limited - 0.4 +5 v v hv voltage on pin hv - 0.4 +650 v currents i fbctrl current on pin fbctrl - 30 ma i fbaux current on pin fbaux - 1+1ma i pfcsense current on pin pfcsense - 1 +10 ma i fbsense current on pin fbsense - 1 +10 ma i fbdriver current on pin fbdriver duty cycle < 10 % - 0.8 +2 a i pfcdriver current on pin pfcdriver duty cycle < 10 % - 0.8 +2 a i hv current on pin hv - 5 ma tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 19 of 29 nxp semiconductors tea1750 greenchip iii smps control ic [1] equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. [2] equivalent to discharging a 200 pf capacitor through a 0.75 m h coil and a 10 w resistor. 9. thermal characteristics 10. characteristics general p tot total power dissipation t amb <75 c - 0.6 w t stg storage temperature - 55 +150 c t j junction temperature - 40 +150 c esd v esd electrostatic discharge voltage class 1 human body model pins 1 to 13 [1] - 2000 v pin 16 (hv) [1] - 1500 v machine model [2] - 200 v charged device model - 500 v table 3. limiting values continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec test board 124 k/w table 5. characteristics t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when ?owing into the ic; unless otherwise speci?ed. symbol parameter conditions min typ max unit start-up current source (pin hv) i hv current on pin hv v hv >80v; v cc tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 21 of 29 nxp semiconductors tea1750 greenchip iii smps control ic output voltage sensing pfc (pin vosense) v th(ol)(vosense) open-loop threshold voltage on pin vosense 0.35 0.40 0.45 v v start(fb) ?yback start voltage [2] - 1.72 - v v stop(fb) ?yback stop voltage 1.55 1.60 1.65 v v burst(l) low-level burst mode voltage 1.87 1.92 1.97 v v burst(h) high-level burst mode voltage 2.19 2.24 2.29 v v reg(vosense) regulation voltage on pin vosense i o(pfccomp) = 0 2.475 2.500 2.525 v v ovp(vosense) overvoltage protection voltage on pin vosense 2.60 2.63 2.67 v i i(vosense) input current on pin vosense v vosense = 2.5 v 5 45 100 na overcurrent protection pfc (pin pfcsense) v sense(pfc)max maximum pfc sense voltage d v/ d t = 50 mv/ m s 0.49 0.52 0.55 v d v/ d t = 200 mv/ m s 0.51 0.54 0.57 v t leb(pfc) pfc leading edge blanking time 250 310 370 ns i prot(pfcsense) protection current on pin pfcsense - 50 - - 5na soft start, soft stop pfc (pin pfcsense) i start(soft)pfc pfc soft start current - 75 - 60 - 45 m a v start(soft)pfc pfc soft start voltage 0.46 0.50 0.54 v v stop(soft)pfc pfc soft stop voltage 0.42 0.45 0.48 v r start(soft)pfc pfc soft start resistance 12 - - k w oscillator pfc f sw(pfc)max maximum pfc switching frequency 100 125 150 khz t off(pfc)min minimum pfc off-time 1.1 1.4 1.7 m s valley switching pfc (pin pfcaux) ( d v/ d t) vrec(pfc) pfc valley recognition voltage change with time - - 1.7 v/ m s t vrec(pfc) pfc valley recognition time v pfcaux = 1 v; peak-to-peak [3] - - 300 ns demagnetization to d v/ d t = 0 [4] --50ns t to(vrec)pfc pfc valley recognition time-out time 346 m s table 5. characteristics continued t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when ?owing into the ic; unless otherwise speci?ed. symbol parameter conditions min typ max unit tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 22 of 29 nxp semiconductors tea1750 greenchip iii smps control ic demagnetization management pfc (pin pfcaux) v th(comp)pfcaux comparator threshold voltage on pin pfcaux - 150 - 100 - 50 mv t to(demag)pfc pfc demagnetization time-out time 40 50 60 m s i prot(pfcaux) protection current on pin pfcaux v pfcaux =50mv - 75 - - 5na driver (pin pfcdriver) i src(pfcdriver) source current on pin pfcdriver v pfcdriver =2v - - 0.5 - a i sink(pfcdriver) sink current on pin pfcdriver v pfcdriver = 2 v - 0.7 - a v pfcdriver =10v - 1.2 - a v o(pfcdriver)max maximum output voltage on pin pfcdriver - 1112v overvoltage protection ?yback (pin fbaux) i ovp(fbaux) overvoltage protection current on pin fbaux 279 300 321 m a n cy(ovp) number of overvoltage protection cycles 6812 demagnetization management ?yback (pin fbaux) v th(comp)fbaux comparator threshold voltage on pin fbaux 60 80 110 mv i prot(fbaux) protection current on pin fbaux v fbaux =50mv - 50 - - 5na v clamp(fbaux) clamp voltage on pin fbaux i fbaux = - 500 m a - 1.0 - 0.8 - 0.6 v i fbaux = 500 m a 0.5 0.7 0.9 v t sup(xfmr_ring) transformer ringing suppression time 1.5 2 2.5 m s pulse width modulator ?yback t on(fb)min minimum ?yback on-time - t leb(fb) -ns t on(fb)max maximum ?yback on-time 20 25 30 m s oscillator ?yback f sw(fb)max maximum ?yback switching frequency 100 125 150 khz v start(vco)fbctrl vco start voltage on pin fbctrl 1.3 1.5 1.7 v v hys(fbctrl) hysteresis voltage on pin fbctrl -60-mv d v vco(fbctrl) vco voltage difference on pin fbctrl - - 0.1 - v table 5. characteristics continued t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when ?owing into the ic; unless otherwise speci?ed. symbol parameter conditions min typ max unit tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 23 of 29 nxp semiconductors tea1750 greenchip iii smps control ic peak current control ?yback (pin fbctrl) v fbctrl voltage on pin fbctrl for maximum ?yback peak current 1.85 2.0 2.15 v v to(fbctrl) time-out voltage on pin fbctrl enable voltage - 2.5 - v trip voltage 4.2 4.5 4.8 v r int(fbctrl) internal resistance on pin fbctrl -3-k w i o(fbctrl) output current on pin fbctrl v fbctrl =0v - 1.4 - 1.17 - 0.93 ma v fbctrl =2v - 0.6 - 0.5 - 0.4 ma i to(fbctrl) time-out current on pin fbctrl v fbctrl = 2.6 v - 36 - 30 - 24 m a v fbctrl = 4.1 v - 34.5 - 28.5 - 22.5 m a valley switching ?yback (pin hv) ( d v/ d t) vrec(fb) ?yback valley recognition voltage change with time - 75 - +75 v/ m s t d(vrec-swon) valley recognition to switch-on delay time [5] - 150 - ns soft start ?yback (pin fbsense) i start(soft)fb ?yback soft start current - 75 - 60 - 45 m a v start(soft)fb ?yback soft start voltage 0.43 0.49 0.54 v r start(soft)fb ?yback soft start resistance 12 - - k w overcurrent protection ?yback (pin fbsense) v sense(fb)max maximum ?yback sense voltage d v/ d t = 50 mv/ m s 0.49 0.52 0.55 v d v/ d t = 200 mv/ m s 0.52 0.55 0.58 v t leb(fb) ?yback leading edge blanking time 255 305 355 ns driver (pin fbdriver) i src(fbdriver) source current on pin fbdriver v fbdriver =2v - - 0.5 - a i sink(fbdriver) sink current on pin fbdriver v fbdriver = 2 v - 0.7 - a v fbdriver =10v - 1.2 - a v o(fbdriver)(max) maximum output voltage on pin fbdriver - 1112v latch input (pin latch) v prot(latch) protection voltage on pin latch 1.23 1.25 1.27 v i o(latch) output current on pin latch v prot(latch) tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 25 of 29 nxp semiconductors tea1750 greenchip iii smps control ic fig 14. typical application diagram of tea1750 12 11 9 16 13 8 6 7 3 2 10 4 1 tea1750t 014aaa021 q r s2 r ss2 c ss2 d2 c out t2 r aux2 r sense2 c vcc 5 r s1 c bus d1 s1 c ss1 r ss1 r sense1 c timeout r loop compensation r aux1 s2 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 26 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 12. package outline fig 15. package outline sot109-1 (so16) x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1 tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 27 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 13. revision history table 6. revision history document id release date data sheet status change notice supersedes tea1750_2 20081215 product data sheet - tea1750_1 modi?cations: value for t j in t ab le 3 has been updated tea1750_1 20070406 product data sheet - - tea1750_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 december 2008 28 of 29 nxp semiconductors tea1750 greenchip iii smps control ic 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 14.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 14.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. greenchip is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. nxp semiconductors tea1750 greenchip iii smps control ic ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 december 2008 document identifier: tea1750_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.3 pfc green features . . . . . . . . . . . . . . . . . . . . . 1 2.4 flyback green features . . . . . . . . . . . . . . . . . . . 2 2.5 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 general control . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 start-up and undervoltage lock-out . . . . . . . . . 5 7.1.2 supply management. . . . . . . . . . . . . . . . . . . . . 7 7.1.3 latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.1.4 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.5 overtemperature protection (otp) . . . . . . . . . . 8 7.2 power factor correction circuit. . . . . . . . . . . . . . 8 7.2.1 t on control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2.2 valley switching and demagnetization (pfcaux pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2.3 frequency limitation . . . . . . . . . . . . . . . . . . . . . 9 7.2.4 mains voltage compensation (vinsense pin). 9 7.2.5 soft start-up (pin pfcsense) . . . . . . . . . . . . . 9 7.2.6 burst mode control . . . . . . . . . . . . . . . . . . . . . 10 7.2.7 overcurrent protection (pfcsense pin) . . . . 11 7.2.8 mains undervoltage lock-out / brownout protection (vinsense pin). . . . . . . . . . . . . . . 11 7.2.9 overvoltage protection (vosense pin) . . . . . 11 7.2.10 pfc open loop protection (vosense pin) . . 11 7.2.11 driver (pin pfcdriver) . . . . . . . . . . . . . . . . 12 7.3 flyback controller . . . . . . . . . . . . . . . . . . . . . . 12 7.3.1 multi mode operation . . . . . . . . . . . . . . . . . . . 12 7.3.2 valley switching (hv pin) . . . . . . . . . . . . . . . . 13 7.3.3 current mode control (fbsense pin) . . . . . . 14 7.3.4 demagnetization (fbaux pin) . . . . . . . . . . . . 15 7.3.5 flyback control / time-out (fbctrl pin) . . . . 15 7.3.6 soft start-up (pin fbsense) . . . . . . . . . . . . . 16 7.3.7 maximum on-time . . . . . . . . . . . . . . . . . . . . . . 17 7.3.8 overvoltage protection (fbaux pin). . . . . . . . 17 7.3.9 overcurrent protection (fbsense pin) . . . . . 18 7.3.10 driver (pin fbdriver). . . . . . . . . . . . . . . . . . 18 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 9 thermal characteristics . . . . . . . . . . . . . . . . . 19 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 19 11 application information . . . . . . . . . . . . . . . . . 24 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 27 14 legal information . . . . . . . . . . . . . . . . . . . . . . 28 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 14.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15 contact information . . . . . . . . . . . . . . . . . . . . 28 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 |
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